There are many important and widespread changes occurring in chip designs, particularly SoC and processor designs that are proving to be the next exciting, positive disruptive architectural IC trend for the semiconductor industry. These chip-level changes truly bridge the ongoing push of ever-improving architectures with user device trends and demands.
AMD's president and CEO, Rory P. Read, recently stated, "The next era of the semiconductor industry will be defined by 'the convergence of technologies and devices,'" (as cited here by ElectroIQ). The truth of this statement is evident in today’s market, as we see user preferences for smaller, portable, connected devices that act as both phone and computer. And, ubiquitous connectivity has become the wireless product feature consumers and business users demand most. Users are searching for the perfect device to seamlessly connect anywhere and handle the mobile computing they demand (that is, enable machine-to-machine [M2M] connectivity to handle the vast amounts of data that users generate, manipulate, and then need to store).
While smaller and lighter form factors leave less and less room for product differentiation based on look and feel, increasingly rich feature offerings and the quest for better and better connectivity open the door for greater differentiation on the software and semiconductor fronts. Chipset design and architecture are changing. Specific changes include: the relationships between software and hardware in the design roadmap for devices; the increasingly heterogeneous structure and complexity of chips; and the rise of complex application specific integrated circuit (ASIC) designs for the system on chip (SoC) market, which is set to boom with the adoption of 2.5D and 3D stacking.
Product differentiation is increasingly defined by substance over style. It's what's inside devices that is driving new features and that offers an excellent outlook for semiconductors.
Driving opportunities in chip design
Complex chips were certainly at the fore during the first quarter of the year (1Q12), not only at the recent Consumer Electronics Show (CES) and Mobile World Congress (MWC), but also with Apple's early March unveiling of the new iPad. At the top of the feature and design lists, OEMs have been touting multi-core processors to provide improved performance, reduced latency, and faster connectivity and data transfer, while providing the best battery life they can.
To meet users' demands for device improvements and the increased pace for device refresh cycles, it has been an engineering necessity to address the issues of power management and heat dissipation (see last quarter's MarketWatch Quarterly article here for details on heat and power issues).
Along the path to addressing the power and heat issues with users' growing feature demand list and keeping to the smaller real estates, there has been a steady move to 3D stacking and heterogeneous SoCs and multi-core processors (see for example this discussion of ASIC and SoC changes from System-Level Design Community). Leading-edge devices are now running on increasingly complex chips, meaning there is more heterogeneous integration of various processors, baseband chips, memory, and logic into single chipsets. Stacking and grouping has become the norm for addressing higher data transfer requirements with lower latency and with an eye to low-power and reduced heat issues. The choices made in how to best integrate functions, both from the engineering of the hardware and the software solution perspectives, has opened the door to many new avenues for competitive differentiation with system-level design options.
Of note, though, is an important challenge still facing the industry in the move to stacked solutions: the need to optimize design integration and develop (or improve) tools to test these complex chipsets. As Michael McNamara of Cadence Design Systems offered in this interview with System-Level Design Community, the industry not only needs new system-level design tools, but also a new way for software and device design to work together. No longer can designs be done in isolation; rather, we must have software-hardware testing and design integration throughout the device build. With more heterogeneous, multi-core, and stacked chips we must also recognize that there is a merging of software and hardware at an intrinsic level; we now must have system-level models of the whole system (see this discussion from Chip Design Magazine and this summary of AMD's SoC roadmap from Solid State Technology). But herein is also an important opportunity for new diversification and competition in semiconductor design: while the largest chip manufacturers continue to grow, and costs continue to climb, these new heterogeneous chipsets require more integration work. The complexity of integrating, testing, and verifying complex chipsets is likely to change the semiconductor supply chain in new ways, as well as likely proliferating fully integrated and tested subsystems. As this recent discussion in System-Level Design Community offers, the shape and role of the SoC is driving significant changes in integrated systems:
Increasingly, [SoC] will be combined into fully integrated systems that include IP, possibly processors, and perhaps even shared resources such as memory with standardized interfaces. That approach will become particularly useful when chips can be stacked, either in 2.5D or 3D, and it will completely render the number of design starts meaningless. There will be more design starts, but the final outcome may be subsystems rather than chips – or chips that are part of a stack rather than the fully integrated stack itself.
"What's changed is the user experience is now a combination of hardware and software," said Mike Gianfagna, vice president of marketing at Atrenta. "We're seeing the consumerization of electronics. The idea isn't new. Joe Costello was talking about this a decade ago. But it's finally happening. The semiconductor content is enabling the user experience."
Wider industry impacts of chip design changes
While the complexity of SoCs increases and the architectural, engineering, integrating, and verification challenges (and standards agreements) are still being worked out, OEMs are obviously moving forward with full-market releases of leading-edge devices to meet (as best as possible) users' demands. The most recent of these device roll-outs were the early March release by Apple of the new iPad and Acer's roll-out of the Iconia Tab A510, an Android tablet running on NVIDIA's Tegra 3 quad-core processor. What we see in the latest round of devices, including these most recent tablets, is the growing importance of complex chips, both multi-core and based on 4x-nm node (Acer's use of NVIDIA's quad-core and Apple's A5X dual-core processors) and complex chipsets with integrated processing, logic, baseband, and other functionality.
The leading-edge devices, smart wireless devices, are where we find the best examples of the recent convergence of device and complex technology, to refer back to AMD's CEO Rory Read. While there is certainly a convergence of device and technology, as we discussed above (particularly at the system-level design and the software-hardware interface), the point of convergence can also be understood as an important differentiation opportunity. And, where we find differentiation, we can also find new opportunities for providing these differentiations along the semiconductor and electronics supply chain.
When it comes to differentiation, Apple has certainly made its mark, and so we'll look more closely at its latest processor architecture. One of the many interesting facts about Apple's new A5X processor is one that has greater importance than meets the eye. Namely, Apple has increased die size in going from the A5 to the A5X, going from 10.1mm x 12.1mm to 12.8mm x 12.7mm, which is 41sq mm bigger (see Credit Suisse [CS], "Rising Silicon Intensity," March 18, 2012). Why is die size important? There are a number of opportunities for growth and new competitive market moves that we can begin to portend for the semiconductor industry based on die size increases, integrated architectures, and the expected volume of mobile devices (tablets as well as smart- and superphones). The following is an abbreviated list of some of the perhaps not so apparent supply chain opportunities that arise from the latest chip designs (taken from both the CS report on the positive industry impact of rising silicon intensity as well as Smith's own insight):
- Increased die size means more wafers, which means more CAPEX for fab equipment "[CS] estimate[s] that Samsung has spent a cumulative $3bb more in CAPEX due to the larger die sizes at Apple." (CS, ibid., p.2)
- Increased die size also underscores the importance of graphics capability because "graphics has always been extremely transistor intensive. […] As graphics is becoming a big differentiator for tablets, the result is that transistor content is sharply rising for tablets." (CS, ibid, pp.2-3)
- The importance of baseband solutions has grown and, with LTE and 4G moving into the mainstream, we expect to see more of the larger baseband chips, such as the larger one from Qualcomm in the New iPad.
- SoC integration provides significant improvements, and this trend is definitely continuing and expanding, leading to new, interesting changes in architecture and design engineering as more and more is housed together and more fabless companies are able to increase or provide new design services.
- Additionally, Apple's new A5X processor is still at the 4x-nm node, in part because of various yield and other bumps holding back the 2x-nm nodes from full ramp, but holding steady at 4x-nm also opens the doors to more competition since we're not dealing with the astronomical costs of leading-edge nodes. (Note: TSMC has stated that they expect volume production at 28nm to ramp up in 2H12 and 3-D IC assembly launch in 2013; see this ElectronicsWeekly report and this EETimes report).
Chip design changes drive new supply chain opportunities
The changes in processor integration and stacking and the development of increasingly integrated, heterogeneous, and complex chips are certain to be positive disruptive events for the semiconductor industry. Not only do we see changes that are driving opportunities for fabless and fab-light companies for new system-level design tools, new verification and validation methods (and standards), closer integration and design work between software and hardware design teams, IP reusability, and other integration and optimization requirements to make the latest complex chipsets successful in the intended devices, but there are also growth opportunities for others along the semiconductor supply chain.
Other important supply chain data can be gleaned from watching processor and SoC design changes. As Credit Suisse significantly notes in the same March 18 report:
What is happening that is NEW […] is that instead of having 2 chip companies controlling processors (Intel/AMD), you now have over 8 (Apple, Samsung, Intel, Qualcomm, Nvidia, TI, Broadcom, ST, even new companies like HiSilicon). If Moore's law only allows you to shrink once every two years (and even that is stretching out as it is getting harder to shrink), and the degree of competition has increased by a factor over 10x, how can chip companies differentiate their processors from each other? By adding features FASTER than Moore's law.
[…] importantly, […] 40/45nm node took meaningfully longer to reach full volume compared to the 90nm and 65nm nodes. Combine faster design cadence and a slowing Moore's law, the pressure on die size is immense for mobile apps processors. Combine that with rising cost to add capacity for each node, the pressure is even higher for CAPEX to increase. (ibid., pp. 4-5)
An important data point supporting the positive impact of rising silicon intensity and the resultant rise in CAPEX for equipment is found in the most recent SEMI book-to-bill data for February 2012. The data indicate the first return to parity in the book-to-bill ratio since September 2010 for North American semiconductor equipment, as reported here by SEMI. Additionally, in the SEMI release, Denny McGuirk, president and CEO of SEMI, stated, "Investments in advanced process technologies for NAND Flash, microprocessor, and foundry are key spending drivers for the year."
There are many chip design integrations taking place (such as the integration of baseband solutions as we're hearing announcements about from Intel) and the driver is rooted in the hottest devices, which continue to be smart wireless devices that support connectivity and mobile computing. While the increase in complex, highly-integrated chipsets is part of the technological solution, the wider semiconductor supply chain impact is broadly-based and moves the semiconductor and electronics industry squarely into a growth position from 2H12 forward, based on the combination of positive macroeconomic forecasts and the positive disruptive innovation from the successful convergence of devices and technology.