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What the Latest Devices Can Tell us about Chip Forecasts


Nope, this is not a post about the next insider scoop, nor is it really about which chips will be hot and which won't.  But wait, there is something very interesting that the recent slew of teardowns and IC mulling over next gen processors are telling us – it's about size, die size and component design trends.

We've all been watching and reading, curious to know about the bill of materials (BoM) for the New iPad, and what's under the hood.  We know it weighs more, but similar in shape and size, so what's in there of interest?  Of particular interest is the new Apple A5X processor (see the fantastic research piece from Credit Suisse (CS), "Rising Silicon Intensity," 18 March 2012).  One of the many interesting facts about the new A5X is one that has greater importance than meets the eye.  Namely, Apple has increased die size in going from the A5 to the A5X, going from 10.1mm x 12.1mm to 12.8mm x 12.7mm, which, CS notes, is 41sq mm bigger.

Okay, okay, so why is die size increase so interesting and why keep reading?  After all, die size wasn't on Apple's cool features list.  There are important and widespread changes occurring in chips, particularly system on chip (SoC) and processor designs which are quickly becoming pervasive.  This chip level change ties together the path of wider architectural change with user device trends and changes.  As AMD's president and CEO, Rory P. Read, recently summarized in his statements about AMD's SoC strategy, "The next era of the semiconductor industry will be defined by "the convergence of technologies and devices,"" (as cited here by ElectroIQ).  Die size matters because as we watch and map the path forward for components, particularly for processors of all types, and we consider the many integrations taking place (such as the integration of a baseband solutions as we're hearing announcements about from Intel) we also must keep in mind the obvious driver, mobile/wireless devices.

The differentiator for the end-product devices are many, certainly, but considering the features of the processors, baseband, battery life, and similar core components is what will make the final decision possible for consumers and enterprises.  So, why is die size important?  There are a number of critical points we can begin to portend for the semiconductor industry based on these size increases and the expected volume of the iPad, as well as the follow-on competition.  Summarizing the CS report, we recognize the following trends in our industry:

  • Increased die size means more wafers which means more CAPEX for fab equipment ("[CS] estimate[s] that Samsung has spent a cumulative $3bb more in CAPEX due to the larger die sizes at Apple." (CS, ibid., p.2)
  • Increased die size also underscores the importance of graphics capability because "graphics has always been extremely transistor intensive. […] As graphics is becoming a big differentiator for tablets, the result is that transistor content is sharply rising for tablets." (CS, ibid, pp.2-3)
  • The importance of baseband solutions has grown and with LTE and 4G moving into the mainstream, we expect to see more of the larger base band chips such as the larger one from Qualcomm in the New iPad.
  • SoC integration provides significant improvements and this trend is definitely continuing and expanding leading to new, interesting changes in architecture and design engineering as more and more is housed together.
  • Additionally, Apple's new A5X processor is still at the 45nm node, in part because of various yield and other bumps holding back the 2xnm nodes from full ramp, but holding steady at 45nm also opens the doors to more competition since we're not dealing with the astronomical costs of leading-edge nodes.

The changes in processors and complex chips is an important and leading edge trend to watch for the semiconductor industry.  Die size is one variable that provides data as to which directions the OEMs are taking as we move forward with new devices and designs.  But there are also important supply chain data to be gleaned from watching processor and SoC design changes.  As Credit Suisse importantly notes in the same 3/18/12 report:

"What is happening that is NEW […] is that instead of having 2 chip companies controlling processors (Intel/AMD), you now have over 8 (Apple, Samsung, Intel, Qualcomm, Nvidia, TI, Broadcom, ST, even new companies like HiSilicon).  If Moore's law only allows you to shrink once every two years (and even that is stretching out as it is getting harder to shrink), and the degree of competition has increased by a factor over 10x, how can chip companies differentiate their processors from each other?  By adding features FASTER than Moore's law." (ibid., p.4)

"[…] importantly, […] 40/45nm node took meaningfully longer to reach full volume compared to the 90nm and 65nm nodes.  Combine faster design cadence and a slowing Moore's law, the pressure on die size is immense for mobile apps processors.  Combine that with rising cost to add capacity for each node, the pressure is even higher for CAPEX to increase." (ibid., p. 5)

There is more to understand about the relationship of component trends and device demand; to read more, watch for Smith's upcoming MarketWatch Quarterly due out the end of this month to subscribers (free subscription available), or later in April to the wider public.

Lisa Ann Cairns, Ph.D.
Written on Wednesday, 21 March 2012 10:13 by Lisa Ann Cairns, Ph.D.

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