A much touted technological revolution is taking place with the migration to 300mm wafers and 45 nanometer (nm) (even 32nm and 22nm) chip architectures. But the quiet revolution is the business shifts occurring as a result of these complex technologies and architectures which portend changes to the semiconductor industry as significant as the technologies themselves.
With the movement toward 22nm chips and 450mm wafers over the next six to seven years, comes equally fantastic complex designs and manufacturing tools that are requiring (as opposed to recommending) the adoption of design for manufacturing (DFM) tools. DFM is no longer just a topic for engineers; the implementation of DFM is changing business models and relationships from foundries to OEMs. In turn, these relationship changes are likely to have significant effects on the entire semiconductor industry as new market structures arise.
This article will review the demand side of the migration to smaller chip architectures, the significant changes and advantages to the new chip and wafer size technologies, along with the resulting changes to business relationships and marketplace dynamics.
The business case for smaller architectures
Many in the electronics industry question the rapid pace of migrations to smaller and smaller chip architectures. While there are obvious arguments for smaller chip sizes such as greater memory, speed, and power performance in laptops based on the device’s real estate, the main demand drivers are not coming from the typical computing end-market. After all, the computing power available to the general consumer is considerably more advanced than what most end-users require to run the average set of programs.
Powerful, high-end graphics microchips are at the fore of the suppliers’ response to market demand for significantly improved graphics capabilities in end-users’ electronics devices (from PCs and laptops to smart phones and digital cameras). The competition at the supplier end is certainly heating up as companies such as Nvidia, with foundry partners TSMC and UMC, ready the release of new chips and motherboard graphics processing units (mGPUs) along side Intel’s new releases this month. A September 2007 EDN article noted that the growing end-market in sophisticated graphics requirements (gaming and image manipulation, among others) is creating opportunities for companies like Nvidia to compete directly with leading chip designers such as Intel and the AMD-ATI graphics alliance. Downstream, an obvious advantage to this increasing competition is the likely reduction in ASP of graphics cards.
Another business partnership that has formed to meet market demand while pooling resources to compete against industry leaders such as Intel, is ARM’s “collective” of semiconductor companies. The Cortex-A9 (single- and multi-core) is ARM’s latest release of new processor designs for the mobile market (to arrive in products by 2010, according to a October 2007 Register Hardware story). Indeed, just as graphics capabilities are driving the migration of architectures, so is the increasingly sophisticated mobile users’ demand for improved capabilities in their ‘ultra mobile devices’ (i.e., mobile phones, digital music and video devices, digital cameras, etc.) Samsung is among those answering this call as they recently unveiled a 64GB NAND flash memory chip based on 30nm architectures. Also among the new developments available for mobile at 45nm and lower are the new HD-SIM™ card solutions that are coupled with new Flash memory solutions, such as the Spansion-ARM integrated solution set.
The opportunities for new memory solutions presented by 45nm and lower architectures extend beyond mobile applications to rack and blade servers and solid state drives (SSDs). NAND flash suppliers are in stiff competition for market share and leadership in the present technological race, which will likely have significant pricing ramifications. NAND is certain to see the greatest transformation as a result of sub-45nm architectures, particularly as “[f]uture NAND products are geared for a new wave of applications, especially solid-state storage drives. […] As a result [of premium pricing now] many analysts said that solid-state storage drives will not hit the mainstream market until 2011.” Another application for the new NAND flash memory will also be seen in set-top boxes (e.g., video-recorders).
65nm may still be ramping, but 45nm is here
45nm is here, albeit not quite for ‘the masses.’ Intel recently released the 45nm Penryn processor architecture for server and high-end desktop products. The mobile Penryns, also part of the Silverthorne family, are not expected until first and second quarters of 2008. In competition with Intel is AMD, who recently announced the start of production of their 45nm processors during the first half of next year.
The initial projections that 65nm technology will be widely used are likely to be borne out, but at a slower pace than forecasted. An important ramification of this news is the balance of chips available in the marketplace. While 45nm chips are forecast for wider production during 2008, the number of chip suppliers will be significantly limited to the market leaders, thereby also affecting the ASPs, since supply will be constrained. A sign of the slower migration to 65nm, according to a September 2007 EDN article, is that many in the industry believe most chip designers, particularly those still at 120nm or above, are waiting to see the direction of the new architectures and will likely skip over intermediate points and begin designing at 45nm. As a result, there are high hopes for the migration to 45nm. Furthermore, for those who have already engaged the 65nm processes, the EDN piece says, moving to 45nm is “fairly straightforward” and therefore not as costly as from 90nm or higher. However, a few other issues are determining the ability to design at the 45nm and smaller levels. This EDN piece goes on to say that as design moves down to 45nm and below, the incredible complexity of the architecture necessitates a move to requiring design for manufacturing (DFM) tools as well as foundries’ adoption of restrictive-design rules (RDRs) “to help design teams produce good IC yields”. The ramification of this seemingly benign though cumbersome requirement goes far beyond the realm of engineers and chip designers and has already begun to change the market structure of the semiconductor industry.
Significant barriers to entry are now further limiting which fabs can migrate at the lightning pace of technological redesigns. Not only are skyrocketing costs for retooling a real variable, but the alliances necessary to work with chip designers are becoming the luxury of the biggest and most powerful fabs. Downstream, OEMs are likely to experience a limiting variable in the supply of chips based on architecture. This type of reduction in competition will reverberate into real costs and profit margins realized for specific products.
Will a side-effect of DFM tools be a reduction of suppliers?
While it may seem like an odd cause and effect scenario, the requirement of DFM tools by the foundries is adding momentum to the shift in business relationships among the leading technology companies. DFM tools are changing everything; the nature of the tools and the level of data sharing required break down the traditional barriers between the previously distinct realms of design and manufacturing, according to a December 2005 EDN article. The article says the reason for this dramatic change is that in order to provide useful DFM tools, foundries must “expose their proprietary manufacturing techniques, their most closely held intellectual property”. Furthermore, EDN Executive Editor Ron Wilson recently noted in his blog that the relationship between suppliers and foundries are changing as leading chip suppliers become more sensitive to cost pressures at the new architectures and may choose to work directly with the foundry, bypassing the fabless semiconductor houses.
Luckily for the foundries, while they may now be in a position where significant amounts of proprietary information must be shared in the form of DFM tools, the enormous expense involved in designing these leading-edge chips also necessitates a new business alliance between foundries, manufacturers, third party IP suppliers, and chip designers. These alliances are changing the industry. Since it is primarily the leading edge designers who are forming these alliances with leading edge foundries and intermediate businesses, the big players are only getting bigger.
This does not mean that mid- and small-sized companies and fabs are unable to compete, it means there is a market separation that is widening. The smaller fabs and mid- to small-sized company alliances are necessarily moving to niche markets, such as analog IC or low- to mid-priced electronics, where the maturing technologies and the architectures that they offer are key to product strategies (e.g., mid- to low-cost, high volume, rapid time to market, etc.). Meanwhile, the leading edge alliances have pooled the capital to pursue the research and development frontier which, in turn, defines them as technological leaders, hence market share leaders in the industry.
Change is the constant
If market concentration results, there will be significant changes to the current dynamics of the chip market. As the number of suppliers compartmentalizes along architectural lines such that for any given leading edge chips (beyond 65nm) only the biggest will have supply since they were the only ones able to fund and demand the migration. As the supplier pool for individual chips shrinks, any single supplier’s actions is likely to have a significant impact on both prices and on the competitive landscape. In this manner, the seemingly minor role of DFM tools, when coupled with the pace of advancement in chip architecture and wafer size, is likely to change the business and economic dynamics of the semiconductor industry over the next seven to ten years.
Internal industry dynamics aside, one thing is certain: change is the constant. 45nm and below is already here as is 300mm and 450mm, and there are serious and economically powerful drivers for this technology. How businesses, either individually or as competing consortia, conquer the exponential cost increases and new complexities that shrinking architectures and new wafer sizes hold, is the remaining question. At this point, there are significant market re-alignments that point to exciting competitive moments and new product offerings.
Associated Press, October 22, 2007, “Samsung Develops New Flash Memory Chip”, http://ap.google.com/article/ALeqM5ggBYhqTVjJ8tBp7oVJWbgRc8RXIQD8SENIUG0.
James, Geoffrey, December 1, 2005, “Virtual versus vertical”, in EDN online, www.edn.com/index.asp?layout=articlePrint&articleID=CA6287343.
Mutschler, Ann S., September 25, 2007, “Nvidia looks to maintain desktop graphics lead with mGPUs”, in EDN online, www.edn.com/index.asp?layout=articlePrint&articleID=CA6482616.
Santarini, Michael, September 13, 2007, “How low can you go? A look at 45-nm-IC-design challenges”, in EDN online, http://www.edn.com/article/CA6475006.html.
Spansion Press Release, October 18, 2007, “Spansion Licenses ARM SecurCore Processor for MirrorBit(R) HD-SIM(TM) Applicability at 45nm and Below”, http://investor.spansion.com/releasedetail.cfm?ReleaseID=269915.
Vance, Ashlee, October 3, 2007, “ARM to bash 'non-issue' Intel with multi-core chip”, in Register Hardware online, www.reghardware.co.uk/2007/10/03/arm_cortex_a9_intel/.
Wilson, Ron, October 3. 2007, “IP, SoC design, and the system OEM: changing roles and a Microsoft view of the future”, in EDN online, http://www.edn.com/blog/1690000169/post/1280015328.html?text=&text=%22IP%2C+SoC+design%2C+and+the+system+OEM%22.